14. Coprocessor 0
14.26 CP0 Move Instructions
The R10000 processor implements Coprocessor 0 move instructions, MTC0, MFC0, DMTC0, and DMFC0, exactly the same as in the R4400 processor, even though some operations are undefined during certain conditions. The exact operations of CP0 move instructions on 32/64-bit CP0 registers are summarized Table 14-26.
Table 14-26 CP0 Move Instructions
The returned value of MFC0/DMFC0 from a non-existing CP0 register is undefined.
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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